1. Field of the Invention
The present invention relates to a semiconductor device having an input protective circuit and a method of manufacturing the same and, more particularly, to a semiconductor device with a CMOS structure having a pMOS transistor and nMOS transistor and a method of manufacturing the same.
2. Description of the Related Art
In some cases, an excess surge voltage beyond the withstand strength of an internal circuit is applied to the input/output terminal of a semiconductor integrated circuit or the like due to, e.g., static electricity. If this excess surge voltage is directly applied to the internal circuit, the internal circuit is destructed. To cope with this phenomenon, an input protective circuit is inserted between the input/output terminal and the internal circuit to prevent an excess surge voltage applied to the input/output terminal from being applied to the internal circuit.
Recently, high integration densities and high-level functions of semiconductor devices are attained, and demand for a high-performance input protective circuit has arisen accordingly. An attempt has been made to increase the withstand strength of the input protective circuit to improve the driving power.
For example, Japanese Patent Laid-Open No. 7-321320 discloses an offset type MOS transistor having a high withstand strength. This MOS transistor is formed on a p-type semiconductor substrate and has a normal n-type heavily doped diffusion layer on the drain side, and an LDD structure only on the source side.
Japanese Patent Laid-Open No. 6-53497 discloses a CMOS transistor having a low breakdown voltage and a high withstand strength. In this CMOS transistor, the source and drain are respectively formed from a heavily doped diffusion layer, and another heavily doped diffusion layer adjacent to the heavily doped diffusion layer and having an opposite conductivity type.
Japanese Patent Laid-Open No. 6-260638 discloses a COOS transistor having impurity diffusion layers with a low junction withstand strength. In this CMOS transistor, at least one of the source and drain is partially formed from a heavily doped diffusion layer and a lightly doped diffusion layer adjacent to the heavily doped diffusion layer and having the same conductivity type, and the remaining portion is formed from a heavily doped diffusion layer and a lightly doped diffusion layer adjacent to the heavily doped diffusion layer and having an opposite conductivity type.
Japanese Patent Laid-Open No. 6-61438 discloses a CMOS transistor having a high withstand strength. The drain has an LDD structure including a lightly doped diffusion layer and a heavily doped diffusion layer, and additionally, a lightly doped diffusion layer of an opposite conductivity type is formed on the channel side of the lightly doped diffusion layer.
As a method of effectively forming an nMOS transistor and a pMOS transistor in a CMOS transistor, a so-called split gate method has been proposed.
In the split gate method, the gate electrodes of an nMOS transistor and a pMOS transistor are separately formed. A resist mask to be used for patterning is also used for ion implantation in forming a lightly doped n- or p-type diffusion layer as a constituent element of an LDD structure, thereby reducing the labor. This method has received a great deal of attention as a CMOS transistor manufacturing method advantageous in cost.
When a CMOS transistor is to be formed by the split gate method, the CMOS transistor and an input protective circuit may be simultaneously formed. However, with the conventional split gate method, only one n- or p-channel transistor can be formed once. This also applies to the techniques disclosed in the above prior arts, so the conventional split gate method cannot be applied to these prior arts.